Papers

With Tag: Fault Coverage

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Test time reduction in a manufacturing environment by combining BIST and ATE

Hamidreza Hashempour, Fred J Meyer, Fabrizio Lombardi
2002 | 10.1109/DFTVS.2002.1173515

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Optimization problems from feature testing of communication protocols

Mihalis Yannakakis, David Lee
1996

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Dual-encoding BIST design with low power consumption based on clock gating

Jianjun Liu, Enmin Tan
2008 | 10.1109/ICCCAS.2008.4657981

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A BIST scheme for operational amplifier by checking the stable output of transient response

Yuan Jun, Tachibana Masayoshi
2011 | 10.1109/ECCTD.2011.6043816

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Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes

Arnaud Virazel, Felix F Wu, Patrick Girard, L Dilillo, Serge Pravossoudovitch, A Bosio, Xiaoqing Wen, Mohammad Tehranipoor, Wulue Zhao, J G Ma
2010 | 10.1109/DDECS.2010.5491748

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Distributed approach for mitigating coverage loss in heterogeneous wireless sensor networks

Mohamed Younis, Kavin R Kasinathan
2011 | 10.1109/GLOCOMW.2011.6162528

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On-line testing for differential fault attacks in cryptographic circuits

Debdeep Mukhopadhyay
2013 | 10.1109/IOLTS.2013.6604084

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Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components

Alain Greiner, Zhen Zhang, Mounir Benabdenbi
2010 | 10.1109/IOLTS.2010.5560209

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An efficient BIST scheme for high-speed adders

Dimitris Nikolos, Costas Efstathiou, H T Vergos
2003 | 10.1109/OLT.2003.1214372

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Increasing the fault coverage in multiple clock domain systems by using on-line testing of synchronizers

Hans G Kerkhoff, Octavian Petre
2001 | 10.1109/OLT.2001.937826

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Minimizing the number of test configurations for FPGAs

Erik Chmelar
2004 | 10.1109/ICCAD.2004.1382702

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Behavioral synthesis for easy testability in data path scheduling

Wayne Wolf, Tienchien Lee, Niraj K Jha
1992 | 10.1109/ICCAD.1992.279303

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Improving the proportion of at-speed tests in scan BIST

Yuhming Huang, Janusz Rajski, Sudhakar M Reddy, Irith Pomeranz
2000 | 10.1109/ICCAD.2000.896514

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Test generation for path delay faults based on learning

Irith Pomeranz, Sudhakar M Reddy
1993

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Scaling deeper to submicron: on-line testing to the rescue

Michael Nicolaidis, Yervant Zorian
1999 | 10.1109/DATE.1999.761161

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Effective low power BIST for datapaths (poster paper)

Dimitris Gizopoulos, Yervant Zorian, Mihalis Psarakis, Antonis Paschalis, Nektarios Kranitis
2000 | 10.1145/343647.344345

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March tests for word-oriented memories

I B S Tlili, A J Van De Goor
1998 | 10.1109/DATE.1998.655905

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A novel reseeding technique for accumulator-based test pattern generation

Dimitris Nikolos, Dimitris Bakalis, Xrysovalantis Kavousianos
2001 | 10.1145/368122.368145

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On optimizing test strategies for analog cells

J Figueras, Anna Maria Brosa
1999 | 10.1109/GLSV.1999.757384

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