Papers

With Tag: Automatic Test Pattern Generation

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Generalized Partial Test Case Generation Method

Arnaldo Vieira Moura, Lehilton Lelis Chaves Pedrosa
2010 | 10.1109/SSIRI-C.2010.25

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Dual-encoding BIST design with low power consumption based on clock gating

Jianjun Liu, Enmin Tan
2008 | 10.1109/ICCCAS.2008.4657981

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Graph-based functional test program generation for pipelined processors

Nikil Dutt, P P Mishra
2004

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Test pattern generation for the combinational representation of asynchronous circuits

Roland Dobai, Elena Gramatova
2010 | 10.1109/DDECS.2010.5491759

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A Low-Cost Accumulator-Based Test Pattern Generation Architecture

Dimitrios Magos, Ioannis Voyiatzis, Steffen Tarnick
2008 | 10.1109/IOLTS.2008.54

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Scaling deeper to submicron: on-line testing to the rescue

Michael Nicolaidis, Yervant Zorian
1999 | 10.1109/DATE.1999.761161

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Using Problem Symmetry in Search Based Satisfiability Algorithms

Robert K Brayton, Mukul R Prasad, Evgueni Goldberg
2002 | 10.1109/DATE.2002.998261

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Automatic test bench generation for validation of RT-level descriptions: an industrial experience

M Sonza Reorda, Giovanni Squillero, Alberto Manzone, Alessandro Pincetti, Fulvio Corno
2000 | 10.1109/DATE.2000.840300

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Dynamic learning based scan chain diagnosis

Yu Huang
2007 | 10.1109/DATE.2007.364644

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Automatic Timed Test Case Generation for Web Services Composition

Fatiha Zaidi, Mounir Lallali, Ana Cavalli, Iksoon Hwang
2008 | 10.1109/ECOWS.2008.14

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A bridging fault model where undetectable faults imply logic redundancy

Irith Pomeranz, Sudhakar M Reddy
2008 | 10.1109/DATE.2008.4484836

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Multi-Clock DFT architecture for interface characterization and power

2012 | 10.1109/SOCC.2012.6398359

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Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults

Walter Anheier, S A Hasan, Ajoy K Palit
2010 | 10.1109/VLSI.Design.2010.30

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On more efficient combinational ATPG using functional learning

Mariahiro Fujita, Jacob A Abraham, Rajarshi Mukherjee, Donald S Fussell, Jawahar Jain
1996 | 10.1109/ICVD.1996.489467

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Design for strong testability of RTL data paths to provide complete fault efficiency

Hideo Fujiwara, Kewal K Saluja, Toshimitsu Masuzawa, Hiroki Wada
2000 | 10.1109/ICVD.2000.812625

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On improving static test compaction for sequential circuits

Ruifeng Guo, Sudhakar M Reddy, Irith Pomeranz
2001 | 10.1109/ICVD.2001.902648

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Application of Test-View Modeling to Hierarchical ATPG

Kathy Yang, Phong Loi, Arie Margulis, Rahul Shukla, Ken Pham, Nagesh Tamarapalli
2014 | 10.1109/VLSID.2014.26

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A Safe Measurement-Based Worst-Case Execution Time Estimation Using Automatic Test-Data Generation

Jianhui Jiang, Liangliang Kong
2010 | 10.1109/PRDC.2010.28

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A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx

Narayan Prasad, Rubin A Parekhji, Srinath Chakravarthy, Ameet Bagwe, Jais Abraham
2000 | 10.1109/TEST.2000.894233

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Test cycle power optimization for scan-based designs

Augusli Kifli, Yu Huang, Kunhan Tsai, Tingpu Tai, Wutung Cheng
2010 | 10.1109/TEST.2010.5699213

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