Papers

With Tag: Automatic Test Equipment

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Test time reduction in a manufacturing environment by combining BIST and ATE

Hamidreza Hashempour, Fred J Meyer, Fabrizio Lombardi
2002 | 10.1109/DFTVS.2002.1173515

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Test infrastructure design for the Nexperia/spl trade/ home platform PNX8550 system chip

Sandeep Kumar Goel, Steven Oostdijk, T Nguyen, Kuoshu Chiu, Erik Jan Marinissen
2004

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A fully digital controlled off-chip IDDQ measurement unit

Jozef Vanneuville, Miroslav Svajda, Barbara T Straka, Hans A R Manhaeve
1998 | 10.1109/DATE.1998.655904

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Scaling deeper to submicron: on-line testing to the rescue

Michael Nicolaidis, Yervant Zorian
1999 | 10.1109/DATE.1999.761161

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Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction

Jishun Kuang, Zhiqiang You, Yongsheng Cheng
2008 | 10.1109/DELTA.2008.56

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Design of a SOC for low cost IC testing

Roslina Mohd Sidek, Ishak Aris, Rahman Wagiran, L Ali, Mohd Alauddin Mohd Ali
2004 | 10.1109/SMELEC.2004.1620908

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Automating the special service work flow

John M Ackroff
1989 | 10.1109/GLOCOM.1989.64020

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High current DPS architecture for sort test challenge

Jeanpascal Mallet
2002 | 10.1109/TEST.2002.1041846

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Potential solutions for benchmarking issues

Don Sterba
1994 | 10.1109/TEST.1994.527975

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Structured CBIST in ASICS

R B Gage
1993 | 10.1109/TEST.1993.470680

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Design Test: a solution to the problems of ASIC verification

Don Allingham, Dean Vendl, Pat Bashford, Mike Peters
1989 | 10.1109/TEST.1989.82380

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A gate-array-based 666 MHz VLSI test system

Takashi Matsumoto, Jun Saitou, Masahiko Kaneko, Ryozou Yoshino, Yoshihiko Hayashi, Shuji Kikuchi, Takashi Suga
1995 | 10.1109/TEST.1995.529872

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Automatic protocol test suite derivation

Samuel T Chanson, Jinsong Zhu
1994 | 10.1109/INFCOM.1994.337659

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DoD revamps testing organization

IEEE Instrumentation & Measurement Magazine | 2005 | 10.1109/MIM.2005.1502438

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I/sub DDQ/ testing because 'zero defects isn't enough': a Philips perspective

Keith Baker, Bas Verhelst
1990 | 10.1109/TEST.1990.114025

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An optimal test sequence for the JTAG/IEEE P1149.1 test access port controller

Chi W Yau, M U Uyar, Anton T Dahbura
1989 | 10.1109/TEST.1989.82277

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STIL: the device-oriented database for the test development lifecycle

Nathan Biggs
1999 | 10.1109/TEST.1999.805880

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Concurrent test planning

Bethany Van Wagenen, Edward Seng
2010 | 10.1109/TEST.2010.5699255

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